Barry Briggs
9/2/2011 12:24:00 PM
Orson Cart wrote:
> Harald wrote:
>
>> Others have suggested that "c" might be "cc", but there is another
>> possibility.
>>
>> If a Makefile contains a rule such as
>>
>> ..c.o:
>> $(COMPILE) -c $<
>>
>> and COMPILE is not defined, then the command to be executed is just
>> "c", the - taken as an option to ignore any errors. And "c" probably
>> will not be found. In this scenario, the "c" is correct, and you
>> should not change it to "cc". You would instead make sure COMPILE
>> gets
>> defined.
>
> Ah yes, it was something like that: in the Makefile there was some
> such "$COMMAND -c filename" stuff, and the $COMMAND
> was undefined, so it looked like c instead. It is derived from
> some rather large setup scripts that take into account the hardware
> and software, but fell through the cracks in my case.
Great catch, Harald!